Lattice-Based Post-Quantum Key Encapsulation Mechanisms with Hardware-Accelerated Fault-Tolerant Architectures

The rapid advancement of large-scale quantum processors presents an existential threat to classical public-key infrastructure based on integer factorization and discrete logarithms. Transitioning to post-quantum cryptographic (PQC) standards requires high-performance, side-channel-resilient implementations capable of operating on resource-constrained embedded nodes. This paper presents an optimized, hardware-software co-designed accelerator for module-lattice-based key encapsulation mechanisms (ML-KEM). The proposed architecture integrates a domain-specific Number Theoretic Transform (NTT) core with parallelized polynomial arithmetic units and randomized masking countermeasures to mitigate both timing and differential power analysis (DPA) attacks. Implemented on modern FPGA and ASIC testbeds, the accelerator demonstrates a 3.8× throughput improvement in key generation and a 4.2× latency reduction during decapsulation relative to state-of-the-art software baselines, while maintaining strict bounded resource utilization. Comprehensive security evaluations confirm full resilience against second-order power analysis attacks, establishing a scalable foundation for securing future mission-critical telecommunications against quantum adversaries.